MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 21

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Feature Overview—MPCBL0050
Note:
Note:
2.2.2
2.2.3
2.2.3.1
September 2007
Order Number: 318146-001
Using a hard drive on the RTM in some environments may require the use of a heat sink
in order to improve heat dissipation. The heat sink is still under development. Contact
your Intel representative for further details.
For detailed information about a Rear Transition Module, please refer to the Technical
Product Specification for that product. Documents are available at http://
www.intel.com/design/telecom/products/cbp/atca/mpcbl0050/techdocs.htm
Dual-Core Intel® Xeon® 5138 LV 2.13GHz Processor
The MPCBL0050 SBC supports two Dual-Core Intel
processors with 1066 MHz front side bus with the following benefits:
For further details, refer to the Dual-Core Intel
processor Datasheet available at http://www.intel.com.
Chipset
The MPCBL0050 uses the Intel
components:
Although a brief overview is provided in this document, detailed component information
can be found in the documentation for the respective devices. Please refer to the Intel
web page: http://www.intel.com
Intel
The architecture of the Intel
performance and feature set required for servers, with configuration options facilitating
optimization of the platform for workloads characteristic of communication,
presentation, storage, performance computation, or database applications. To
accomplish this, the MCH has numerous RASUM (Reliability, Availability, Serviceability,
Usability, and Manageability) features on multiple interfaces.
The Intel
Dual-Core Intel Xeon 5000 Sequence processor. The Intel 5000P chipset supports two
processors on dual independent point to point system buses operating at 266 MHz
(1066 MTS). The theoretical bandwidth of the two processor busses is 21 GB/s for
Dual-Core Intel Xeon 5100 series. The MCH supports 36 bit addressability for a total 64
GB of physical memory.
In the Intel 5000P chipset-based platform, the MCH provides the processor interface,
fully buffered DIMM memory interfaces, PCI Express* bus interfaces, ESI interface, and
SM Bus interfaces.
• Dual processor support, power-optimized 1066 MT/s front-side bus (FSB), and a
• EM64T technology allowing to expand memory addressing space to 64bit.
• FSB address, data parity, and an enhanced error reporting mechanism through the
• Intel
• Intel
• Intel
4MB shared L2 cache per processor, that enables up to four high-performance cores
per platform
MCA (Machine Check Architecture) that ensures reliability and data integrity
®
5000 Memory Controller Hub
®
®
®
®
5000P Memory Controller Hub (MCH)
6321ESB I/O Controller (ICH)
82571EB Gigabit Ethernet Controller
5000P chipset is designed for use in server systems based on the processor
®
5000P Memory Controller Hub (MCH) provides the
®
5000P chipset which comprises the following major
Intel NetStructure
®
Xeon® 5138 LV 2.13GHz processor
®
Xeon
®
®
MPCBL0050 Single Board Computer
5138 LV 2.13 GHz
Technical Product Specification
21