MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 141

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

EFI BIOS Features—MPCBL0050
6.0
6.1
6.2
6.3
6.4
September 2007
Order Number: 318146-001
EFI BIOS Features
Introduction
The Intel NetStructure
(Extensible Firmware Interface) developed by Intel and AMI*. The EFI BIOS resides in
the Flash ROM. It provides hardware-specific initialization algorithms and standard PC-
compatible basic input / output (I/O) services, and standard Intel® Server Board
features. The Flash ROM also contains firmware for certain embedded devices. These
images are supplied by the device manufacturers and are not specified in this
document.
The EFI BIOS implementation is based on the Intel® Platform Innovation Framework
for EFI architecture and is compliant with all Intel Platform Innovation Framework for
EFI architecture specifications specified in the Extensible Firmware Interface Reference
Specification, Version 1.1.
The EFI displays a message during POST identifying the type of EFI and a revision code.
EFI BIOS Flash Memory Organization
The MPCBL0050 contains two firmware hub (FWH) devices (see
SBC block diagram” on page
code that executes during POST. The second is the backup FWH, which recovers the
system when the primary FWH is corrupted.
Redundant EFI BIOS Functionality
The MPCBL0050 hardware provides two flash devices for EFI BIOS where redundant
copies are stored. Logic to select the active EFI BIOS device is connected to the IPMC.
IPMC firmware selects the EFI BIOS device to boot from.
By default, the firmware selects EFI BIOS device FWH0. The EFI BIOS executes code
from this flash and performs checksum validation of its operational code. This
checksum occurs in the boot block of the EFI BIOS. If the boot block detects a
checksum failure in the remainder of the EFI BIOS, it notifies the IPMC of the failure. In
the event of failure, the IPMC firmware:
Language Support
English is the only supported language.
1. Asserts the RESET pin on the processor.
2. Switches the flash device.
3. Deasserts the RESET pin on the processor, allowing EFI BIOS to execute off the
4. Logs a SEL event
second flash device.
®
MPCBL0050 Single Board Computer uses a Aptio* EFI
18). The first one is the primary FWH, which holds the EFI
Intel NetStructure
®
MPCBL0050 Single Board Computer
Technical Product Specification
Figure 1, “MPCBL0050
141