MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 102

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
5.3.4.3
5.3.5
5.3.6
Intel NetStructure
Technical Product Specification
102
®
BIOS initializes the correctable error counters to a value of 10 for correctable ECC
errors. These counters are on a per-rank basis. A rank applies to a pair of FBDIMMs on
adjacent channels functioning in lock-stepped mode.
As there are 2 ranks per DIMM, logging errors for a single FB-DIMM may be disabled
after detecting 10 to 19 ECC errors.
When the ECC counter for Rank reaches the threshold of 10 errors, BIOS stops logging
records to SEL with sensor type 0Ch (Memory) and a single record is logged to SEL with
sensor type 10h (Logging Disabled) with offset 00h (Correctable Memory Error Logging
Disabled). BIOS adds an entry to the event log to indicate that logging for that type of
error has been disabled. BIOS re-enables logging and SMIs the next time the system is
rebooted.
The system BIOS implements this feature for correctable bus errors. Uncorrectable
Errors
The MCH can also detect uncorrectable errors and generate SMIs to the BIOS. If the
error is in a data area, BIOS generates an event to the IPMC.
If the error is in a code area, BIOS itself may be unresponsive and it may not be
possible to detect whether an uncorrectable error has occurred. In that case, there are
other functionalities in the management subsystem to log payload failure:
Other Memory Events
During board boot, BIOS logs several events about about memory configuration. The
information contains data on slots populated and memory sizes for populated modules.
System Firmware Progress (POST Error)
The EFI BIOS performs a power-on self-test (POST) at initialization. POST examines all
major board components and logs errors if detected to the SEL by generating a System
Firmware Progress (sensor type 0Fh) event. Refer to
errors.
Port 80h POST Codes
As the EFI BIOS goes through its initialization process, it sends progress codes to port
80h. These codes are useful for test debug purposes. For remote management
purposes, the IPMC firmware provides the capability to snoop and capture up to five
consecutive codes written to port 80h. These codes are captured automatically by the
IPMC firmware when the board goes through either cold or warm reset or by an explicit
IPMI command received by the IPMC via the available interfaces (IPMB or KCS). Please
refer to
• The IPMC provides an additional SMI timeout sensor through which IPMC firmware
• An OS or application executing on the processor can set up a watchdog timer with
MPCBL0050 Single Board Computer
continually monitors for SMI assertions and sets a 90-second timeout for clearing
SMI assertions. If an SMI is not cleared within 90 seconds, the IPMC firmware
generates an SMI timeout sensor event. The system manager can set policy for
action to take on an SMI timeout, which can be pre-configured with the IPMC
firmware to generate a blade power down, power cycle, cold reset, or warm reset.
the IPMC. When it times out, a WDT timeout event is sent out and the IPMC takes
the action that has been set up in the WDT (hard reset, power down, power cycle,
or do nothing).
Table Note:
for the POST codes list.
Section 8.1
MPCBL0050—Hardware Management
for the list of possible
Order Number: 318146-001
September 2007