MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 55

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Connectors and LEDs—MPCBL0050
Table 19.
3.6.4
Table 20.
d
Table 21.
September 2007
Order Number: 318146-001
1
2
3
4
5
6
7
8
9
10
Pin
RMD_INT#
SA[0]TX+
SA[2]TX+
Eth0_DA+
Eth1_DA+
Eth0_Link
Reserved
P0_Tx+
P2_Tx+
USB[0]+
A
J30 signal descriptions (Sheet 2 of 2)
Zone 3 Rear Transition Module Data/Control Connector (J31)
The MPCBL0050 SBC implementation includes an RTM connector (J31) that mates
directly to the RTM without connecting through the backplane. The Zone 3 connector
J30 consists of one 120-pin HM-Zd connector with 40 differential pairs, which allows
high-speed signals to be passed between the boards. The signals that are routed
through J31 are the IPMC signals, IEEE 1149.1 JTAG signals, SAS storage ports, USB
2.0 signals, and serial port.
AdvancedTCA RTM connector (Zone 3) J31 Pinouts
J31 signal descriptions (Sheet 1 of 2)
Pin
D1
D2
E1
E2
Pin
A1
B1
C1
D1
E1
F1
G1-H1
TRTST-
SA[0]TX-
SA[2]TX-
Eth0_DA-
Eth1_DA-
Eth0_Act
Reserved
P0_Tx-
P2_Tx-
USB[0]-
Signal
12V
12V
PS1#
ENABLE#
B
Signal
RMD_INT
TRST#
TCLK
TDI
TMS
TDO
RSVD
TCLK
SA[0]RX+
SA[2]RX+
Eth0_DB+
Eth1_DB+
Eth0_Spd10
00
Reserved
P0_Rx+
P2_Rx+
DSR#
C
Comments
12V RTM payload power (short contact); provides power to active devices (other
than management system) on the RTM. See additional requirements below.
Presence Signal, active low (short contact); the RTM connects this signal to
Logic_GND through a 100 Ohm resistor (to facilitate manufacturing test). The SBC
reads this signal to understand if an RTM is fully inserted.
Module enable signal, active low (short contact); the SBC sets this signal high to
reset the RMC (RTM Management Controller).
TDI
SA[0]RX-
SA[2]RX-
Eth0_DB-
Eth1_DB-
Eth1_Link
Reserved
P0_Rx-
P2_Rx-
RXD#
Comments
Reserved
Test Reset signal as defined in JTAG (IEEE 1149.1). The SBC’s main JTAG
chain must connect to this signal.
Test Clock signal as defined in JTAG. Required on SBCs and RTMs with
JTAG-enabled devices.
Test Data In signal as defined in JTAG. SBCs must connect this signal into
the test data chain (that is, in line with TDO connections from other
chips), but must have a means to bypass this connection if an RTM is not
installed.
Test Mode State signal as defined in JTAG. Required on SBCs and RTMs
with JTAG-enabled devices.
Test Data Out signal as defined in JTAG. See TDI comments above.
Output of RTM.
Reserved.
D
TMS
SA[1]TX+
No Connect
Eth0_DC+
Eth1_DC+
Eth1_Act
Reserved
P01_Tx+
P03_Tx+
RTS
E
Intel NetStructure
TDO
SA[1]TX-
No Connect
Eth0_DC-
Eth1_DC-
Eth1_Spd10
00
Reserved
P1_Tx-
P3_Tx-
TXD
F
®
MPCBL0050 Single Board Computer
Reserved
SA[1]RX+
No Connect
Eth0_DD+
Eth1_DD+
PCI_INTA
PCIe_Clk_1+
P1_Rx+
P3_Rx+
CTS#
Technical Product Specification
G
No Connect
SA[1]RX-
No Connect
Eth0_DD-
Eth2_DD-
PCI_RESET
P1_Rx-
P3_Rx-
DTR
PCIe_Clk_1-
H
55