MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 991

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DDRA[7:0]
PB[7:0]
PA[7:0]
Reset
Reset
Field
24.0.5.2
Read: Anytime.
Write: Anytime.
Field
24.0.5.3
Read: Anytime.
Write: Anytime.
Field
7–0
7–0
7–0
W
W
R
R
DDRA7
Port A — Port A pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
PB7
Port B — Port B pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O
pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state
is read.
Data Direction Port A — This register controls the data direction for port A. DDRA determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
Port B Data Register (PORTB)
Port A Data Direction Register (DDRA)
on PORTA after changing the DDRA register.
DDRA6
PB6
0
0
6
6
Figure 24-5. Port A Data Direction Register (DDRA)
Figure 24-4. Port B Data Register (PORTB)
Table 24-5. PORTB Field Descriptions
Table 24-4. PORTA Field Descriptions
Table 24-6. DDRA Field Descriptions
DDRA5
PB5
5
0
5
0
DDRA4
PB4
0
0
4
4
Description
Description
Description
DDRA3
PB3
3
0
3
0
DDRA2
PB2
0
0
2
2
DDRA1
PB1
1
0
1
0
DDRA0
PB0
0
0
0
0