MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 770

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
match condition requires that a valid match for both comparators happens on the same bus cycle. A match
condition on only one comparator is not valid. An aligned word access which straddles the range boundary
will cause a trigger only if the aligned address is inside the range.
20.4.2.3.2
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can
be configured for range comparisons. A single match condition on either of the comparators is recognized
as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned
address is outside the range.
Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are
from an unexpected range. In forced trigger modes the outside range trigger would typically be activated
at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to
$7FFFFF or lower range limit to $000000 respectively.
When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by
the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR
register and hence vector address can be modified.
20.4.3
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the
trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in
the following sections.
20.4.3.1
If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state
sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the
current state determines the next state for each trigger. Forced triggers are generated as soon as the
matching address appears on the address bus, which in the case of opcode fetches occurs several cycles
before the opcode execution. For this reason a forced trigger of an opcode address precedes a tagged trigger
at the same address by several cycles.
20.4.3.2
If either a S12XCPU or XGATE taghit occurs a transition to another state sequencer state is initiated and
the corresponding DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first
generate tags based on comparator matches. When the tagged instruction reaches the execution stage of
the instruction queue a taghit is generated by the S12XCPU/XGATE. The state control register for the
current state determines the next state for each trigger.
20.4.3.3
In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an
instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the
772
Trigger Modes
Forced Trigger On Comparator Match
Trigger On Comparator Related Taghit
External Tagging Trigger
Outside Range (address < CompAC_Addr or address > CompBD_Addr)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor