MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 204

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 XGATE (S12XGATEV2)
6.4.4
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism
to protect system resources that are shared between two concurrent threads of program execution; one
thread running on the S12X_CPU and one running on the XGATE RISC core.
Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked
by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore
register (XGSEM, see
this through its SSEM and CSEM instructions.
Figure 6-21
204
Semaphores
illustrates the valid state transitions.
Section 6.3.1.6, “XGATE Semaphore Register
LOCKED BY
%1
SSEM Instruction
CSEM Instruction
S12X_CPU
XGSEM
Figure 6-21. Semaphore State Transitions
MC9S12XDP512 Data Sheet, Rev. 2.21
UNLOCKED
%0
CSEM Instruction
XGSEM
%1
%0
SSEM Instruction
LOCKED BY
(XGSEM)”). The RISC core does
XGATE
XGSEM
XGSEM
Freescale Semiconductor