MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 178

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.11
Read: Anytime
Write: Anytime
5.3.2.12
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified
in the device overview. The port pins are shared with the analog A/D inputs AN7–0.
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general purpose digital input.
178
Function
PTAD[7:0]
IEN[7:0]
Reset
Reset
Field
Field
7–0
7–0
Pin
W
W
R
R
PTAD7
IEN7
AN7
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled
(IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read
returns the logic level on ANx pin (signal potentials not meeting V
indeterminate value).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD0 bits to “1”.
ATD Input Enable Register (ATDDIEN)
Port Data Register (PORTAD)
0
1
7
7
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
= Unimplemented or Reserved
PTAD6
IEN6
AN6
0
1
6
6
Figure 5-13. ATD Input Enable Register (ATDDIEN)
Figure 5-14. Port Data Register (PORTAD)
Table 5-21. ATDDIEN Field Descriptions
Table 5-22. PORTAD Field Descriptions
PTAD5
MC9S12XDP512 Data Sheet, Rev. 2.21
IEN5
AN5
0
1
5
5
PTAD4
IEN4
AN4
0
1
4
4
Description
Description
PTAD3
IEN3
AN3
0
1
3
3
IL
or V
PTAD2
IH
IEN2
AN2
0
1
specifications will have an
2
2
Freescale Semiconductor
PTAD1
IEN1
AN1
0
1
1
1
PTAD0
IEN0
AN0
0
1
0
0