MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 868

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.56 Port J Data Direction Register (DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4). The
IIC takes control of the I/O if enabled. In these cases the data direction bits will not change.
The SCI2 forces the I/O state to be an output for each port line associated with an enabled output (TXD2).
It also forces the I/O state to be an input for each port line associated with an enabled input (RXD2). In
these cases the data direction bits will not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
870
DDRJ[7:4]
DDRJ[2:0]
Reset
Field
7–0
W
R
DDRJ7
Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTJ or PTIJ registers, when changing the DDRJ register.
= Unimplemented or Reserved
DDRJ6
0
6
Figure 22-58. Port J Data Direction Register (DDRJ)
Table 22-52. DDRJ Field Descriptions
DDRJ5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRJ4
0
4
Description
0
0
3
DDRJ2
0
2
DDRJ1
Freescale Semiconductor
0
1
DDRJ0
0
0