MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 746

MC9S12XDP512MAG

Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S12XDP512MAG

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDP512MAG
Manufacturer:
FREESCALE
Quantity:
5 530
Part Number:
MC9S12XDP512MAG
Manufacturer:
Exar
Quantity:
20
Part Number:
MC9S12XDP512MAG
Manufacturer:
FREESCALE
Quantity:
3 450
Part Number:
MC9S12XDP512MAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDP512MAG
Manufacturer:
FREESCALE
Quantity:
3 450
Chapter 20 S12X Debug (S12XDBGV3) Module
20.3
20.3.1
A summary of the registers associated with the S12XDBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
748
Address
0x0028
0x0028
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0027
0x0029
(See DUG)
(See DUG)
(See DUG)
Pin Name
TAGLO
TAGLO
TAGHI
1
2
Memory Map and Registers
(COMPB/D)
(COMPA/C)
DBGSCRX
DBGXCTL
DBGXCTL
DBGMFR
DBGTCR
DBGCNT
DBGXAH
DBGTBH
DBGTBL
Module Memory Map
DBGC1
DBGSR
DBGC2
Name
Tagging Enable
Pin Functions
Unconditional
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
Table 20-2. External System Pins Associated With S12XDBG
TAGLO
TAGHI
Bit 15
Bit 7
ARM
Figure 20-2. Quick Reference to S12XDBG Registers
Bit 7
TBF
SZE
0
0
0
0
0
0
TSOURCE
MC9S12XDP512 Data Sheet, Rev. 2.21
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
EXTF
Bit 14
Bit 22
TRIG
NDB
Bit 6
SZ
6
0
0
0
0
XGSBPE
Bit 13
Bit 5
TAG
TAG
21
5
0
0
0
0
TRANGE
Bit 12
BDM
Bit 4
BRK
BRK
20
4
0
0
0
0
Description
Bit 11
MC3
Bit 3
CNT
SC3
RW
RW
19
3
0
TRCMOD
DBGBRK
CDCM
Bit 10
SSF2
RWE
RWE
MC2
Bit 2
SC2
18
2
Table
Freescale Semiconductor
SSF1
20-2. Detailed
MC1
SRC
SRC
Bit 9
Bit 1
SC1
17
1
COMRV
TALIGN
ABCM
COMPE
COMPE
SSF0
Bit 16
Bit 0
MC0
Bit 8
Bit 0
SC0

Related parts for MC9S12XDP512MAG