MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 789

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

21.3.2.1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes, the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register controls input pin threshold level and determines the external address and data bus sizes in
normal expanded mode. If not in use with the external bus interface, the related pins can be used for
alternative functions.
External bus is available as programmed in normal expanded mode and always full-sized in emulation
modes and special test mode; function not available in single-chip modes.
Freescale Semiconductor
ASIZ[4:0]
Reset
ITHRS
HDBE
Field
4–0
7
5
W
R
ITHRS
Reduced Input Threshold — This bit selects reduced input threshold on external data bus pins and specific
control input signals which are in use with the external bus interface in order to adapt to external devices with a
3.3 V, 5 V tolerant I/O.
The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable
signals of the EBI pin function as summarized in
0 Input threshold is at standard level on all pins
1 Reduced input threshold level enabled on pins in use with the external bus interface
High Data Byte Enable — This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-bit
data bus can be used with the external bus interface. In this case the unused data pins and the data select
signals (UDS and LDS) are free to be used for alternative functions.
0 DATA[15:8], UDS, and LDS disabled
1 DATA[15:8], UDS, and LDS enabled
External Address Bus Size — These bits allow scalability of the external address bus. The programmed value
corresponds to the number of available low-aligned address lines (refer to
ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when
using alternative functions on relevant pins in applications which utilize a reduced external address bus.
External Bus Interface Control Register 0 (EBICTL0)
0
7
Figure 21-3. External Bus Interface Control Register 0 (EBICTL0)
= Unimplemented or Reserved
0
0
6
Table 21-2. EBICTL0 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
HDBE
1
5
ASIZ4
1
4
Table
Description
21-3.
ASIZ3
1
3
Chapter 21 External Bus Interface (S12XEBIV2)
ASIZ2
1
2
Table
21-4). All address lines
ASIZ1
1
1
ASIZ0
1
0
791