MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 564

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.3.2.6
The Reserved 06 is reserved for test purposes.
14.3.2.7
The Reserved 07 is reserved for test purposes.
14.4
14.4.1
Module VREG_3V3 is a voltage regulator, as depicted in
are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on
reset module (POR), and a low-voltage reset module (LVR).
14.4.2
Respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ
only in the amount of current that can be delivered.
The regulator is a linear regulator with a bandgap reference when operated in Full Performance Mode. It
acts as a voltage clamp in Reduced Power Mode. All load currents flow from input V
V
14.4.2.1
In Full Performance Mode, the output voltage is compared with a reference voltage by an operational
amplifier. The amplified input voltage difference drives the gate of an output transistor.
564
SSPLL
Reset
Reset
W
W
R
R
. The reference circuits are supplied by V
Functional Description
General
Regulator Core (REG)
Reserved 06
Reserved 07
Full Performance Mode
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
Figure 14-8. Reserved 06
Figure 14-9. Reserved 07
DDA
0
0
0
0
4
4
and V
Figure
SSA
0
0
0
0
3
3
.
14-1. The regulator functional elements
0
0
0
0
2
2
Freescale Semiconductor
DDR
0
0
0
0
1
1
to V
SS
or
0
0
0
0
0
0