MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 373

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Read: Anytime
Write: Anytime
8.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: Anytime
Write: Anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the
high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are
concatenated, channel 0 registers become the high order bytes of the double byte channel.
See
Function.
Freescale Semiconductor
CAE[7:0]
Reset
Field
Section 8.4.2.7, “PWM 16-Bit Functions”
7–0
W
R
CON67
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
PWM Control Register (PWMCTL)
0
7
Write these bits only when the corresponding channel is disabled.
Change these bits only when both corresponding channels are disabled.
= Unimplemented or Reserved
CON45
0
6
Figure 8-8. PWM Control Register (PWMCTL)
Table 8-7. PWMCAE Field Descriptions
CON23
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
for a more detailed description of the concatenation PWM
CON01
NOTE
NOTE
0
4
Description
PSWAI
0
3
Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
PFRZ
0
2
0
0
1
0
0
0
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