MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 798

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
21.4.5.2
In emulation modes and special test mode, the external signals LSTRB, R/W, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in
800
Word write of data on DATA[15:0] at an even and even+1 address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word read of data on DATA[15:0] at an even and even+1 address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Indicates No Access
Unimplemented
Word write of data on DATA[15:0] at an even and even+1
address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
Word read of data on DATA[15:0] at an even and even+1
address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
Emulation Modes and Special Test Mode
Table 21-18. Access in Emulation Modes and Special Test Mode
Access
Access
Table 21-17. Access in Normal Expanded Mode
MC9S12XDP512 Data Sheet, Rev. 2.21
R/W LSTRB ADDR0
0
0
0
0
1
1
1
1
RE WE UDS LDS
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
1
Table
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
Out
Out
Out data(odd+1) Out
0
0
1
0
0
1
1
0
1
I/O
21-18.
In
In
In
In
In
DATA[15:8]
Out data(even) Out data(odd)
Out data(even)
I/O data(addr) I/O data(addr)
In
In
In
In
In
In
In
data(odd+1)
data(addr)
data(even)
data(even)
data(even)
data(odd)
DATA[15:8]
data(even)
data(even)
x
x
Freescale Semiconductor
x
x
x
x
x
Out
Out
I/O
In
In
In
In
In
Out data(odd)
In
In
In
In
In
In
In
DATA[7:0]
DATA[7:0]
data(even+1)
data(addr)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
x
x
x
x
x
x
x