MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 839

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.19 Port T Data Direction Register (DDRT)
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare.
In this case the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
Freescale Semiconductor
DDRT[7:0]
Reset
Field
7–0
W
R
DDRT7
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTT or PTIT registers, when changing the DDRT register.
DDRT6
0
6
Figure 22-21. Port T Data Direction Register (DDRT)
Table 22-23. DDRT Field Descriptions
DDRT5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRT4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRT3
0
3
DDRT2
0
2
DDRT1
0
1
DDRT0
0
0
841