MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 1184
MC9S12XDP512MAG
Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512MAG.pdf
(1348 pages)
Specifications of MC9S12XDP512MAG
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another
command write sequence (see
28.5
28.5.1
If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered
command will be completed.
The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled
(see
28.5.2
If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if
the operation is program or erase, the Flash array data being programmed or erased may be corrupted and
the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will
immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set
and any buffered command will not be launched. The ACCERR flag must be cleared before starting a
command write sequence (see
28.5.3
In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all
Flash commands listed in
mode, only mass erase can be executed.
28.6
The Flash module provides the necessary security information to the MCU. After each reset, the Flash
module determines the security state of the MCU as defined in
(FSEC)”.
The contents of the Flash security byte at 0x7F_FF0F in the Flash Configuration Field must be changed
directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is
unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize
to a secure operating mode.
1186
Section 28.8,
Operating Modes
Flash Module Security
Wait Mode
Stop Mode
Background Debug Mode
As active commands are immediately aborted when the MCU enters stop
mode, it is strongly recommended that the user does not use the STOP
instruction during program or erase operations.
“Interrupts”).
Table 28-18
Section 28.3.2.6, “Flash Status Register
Section 28.4.1.2, “Command Write
MC9S12XDP512 Data Sheet, Rev. 2.21
can be executed. If the MCU is secured and is in special single chip
NOTE
Section 28.3.2.2, “Flash Security Register
Sequence”).
(FSTAT)”).
Freescale Semiconductor
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