MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 73

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
Vector base + $CC
Vector base + $EC
Vector base + $DA
Vector base + $CE
Vector base + $CA
Vector base + $F8
Vector base + $E2
Vector base+ $DC
Vector base + $D8
Vector base + $D4
Vector base + $D2
Vector base + $D2
Vector base + $D0
Vector base + $C8
Vector base + $C6
Vector base + $C4
Vector base + $C2
Vector base + $C0
Vector base+ $EE
Vector base+ $EA
Vector base+ $DE
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base+ $E0
Vector base+ $D6
Vector Address
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
$FFFE
$FFFC
$FFFA
1
Channel ID
XGATE
$6D
$6C
$6F
$6E
$6B
$6A
$78
$77
$76
$75
$74
$73
$72
$71
$70
$69
$68
$67
$66
$65
$64
$63
$62
$60
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Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
2
MC9S12XDP512 Data Sheet, Rev. 2.21
System reset or illegal access reset
Enhanced capture timer channel 0
Enhanced capture timer channel 1
Enhanced capture timer channel 2
Enhanced capture timer channel 3
Enhanced capture timer channel 4
Enhanced capture timer channel 5
Enhanced capture timer channel 6
Enhanced capture timer channel 7
Enhanced capture timer overflow
Modulus down counter underflow
Unimplemented instruction trap
Pulse accumulator input edge
Pulse accumulator A overflow
Pulse accumulator B overflow
CRG self-clock mode
COP watchdog reset
Clock monitor reset
Real time interrupt
Interrupt Source
CRG PLL lock
IIC0 bus
Port H
Port J
XIRQ
ATD0
ATD1
SPI0
SCI0
SCI1
SWI
IRQ
Reserved
Reserved
Chapter 1 Device Overview MC9S12XD-Family
Mask
None
None
None
None
None
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
SPI0CR1 (SPIE, SPTIE)
PLLCTL (CME, SCME)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
PIEH (PIEH7-PIEH0)
ATD0CTL2 (ASCIE)
ATD1CTL2 (ASCIE)
PIEJ (PIEJ7-PIEJ0)
CRGINT(LOCKIE)
CRGINT (SCMIE)
IRQCR (IRQEN)
COP rate select
CRGINT (RTIE)
PACTL (PAOVI)
PBCTL(PBOVI)
MCCTL(MCZI)
TSRC2 (TOF)
Local Enable
IBCR0 (IBIE)
PACTL (PAI)
SCI0CR2
SCI1CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
None
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