MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 100

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1):
The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
the maximum system frequency (f
manual mode:
2.4.1.2
100
EXTAL
XTAL
•
•
•
•
•
•
•
•
The TRACK bit is a read-only indicator of the mode of the filter.
The TRACK bit is set when the VCO frequency is within a certain tolerance,
the VCO frequency is out of a certain tolerance,
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance,
when the VCO frequency is out of a certain tolerance,
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in
manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode.
After turning on the PLL by setting the PLLON bit software must wait a given time (t
entering tracking mode (ACQ = 0).
After entering tracking mode software must wait a given time (t
as the source for system and core clocks (PLLSEL = 1).
CONDITION
OSCILLATOR
GATING
System Clocks Generator
= CLOCK GATE
PHASE
LOCK
LOOP
OSCCLK
PLLCLK
MONITOR
CLOCK
Figure 2-17. System Clocks Generator
sys
PLLSEL or SCM
MC9S12XDP512 Data Sheet, Rev. 2.21
) and require fast start-up. The following conditions apply when in
1
0
1
0
SCM
STOP(PSTP,PCE),
STOP(PSTP,PRE),
WAIT(COPWAI),
WAIT(RTIWAI),
COP ENABLE
RTI ENABLE
SYSCLK
STOP
unt
STOP
.
unl
.
2
al
) before selecting the PLLCLK
CLOCK PHASE
GENERATOR
COP
RTI
Freescale Semiconductor
trk
Lock
, and is clear when
, and is cleared
acq
CORE CLOCK
BUS CLOCK
OSCILLATOR
CLOCK
) before