MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 617

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

17.3.2
17.3.2.1
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Freescale Semiconductor
Address
Address: 0x000A PRR
1. ROMON is bit[0] of the register MMCTL1 (see
0x011C
0x011D
0x011E
0x011F
Reset
1
2
W
R
CS3E, CS2E, CS1E, CS0E
Disabled: feature always inactive.
Enabled: activity is controlled by the appropriate register bit value.
RAMWPC
RAMXGU
RAMSHU
RAMSHL
Register
Register Descriptions
Name
MMC Control Register (MMCCTL0)
Register Bit
0
0
7
= Unimplemented or Reserved
W
W
W
W
R
R
R
R
0
0
6
RPWE
Bit 7
1
1
1
Figure 17-3. MMC Control Register (MMCCTL0)
Table 17-3. Chip Selects Function Activity
Disabled
Figure 17-2. MMC Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
= Unimplemented or Reserved
NS
XGU6
SHU6
SHL6
0
0
5
6
0
Figure
1
Disabled
1-10)
XGU5
SHU5
SHL5
SS
5
0
0
0
4
Enabled
XGU4
SHU4
SHL4
NX
4
0
CS3E
Chip Modes
0
3
2
Chapter 17 Memory Mapping Control (S12XMMCV2)
XGU3
SHU3
SHL3
Disabled
3
0
ES
CS2E
0
2
XGU2
SHU2
SHL2
Enabled
2
0
EX
CS1E
0
1
XGU1
SHU1
SHL1
AVIE
1
Enabled
ST
ROMON
CS0E
XGU0
SHU0
SHL0
Bit 0
AVIF
0
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