MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 929

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DDRK[7:0]
Reset
PTT[7:0]
Reset
Field
23.0.5.17 Port T Data Register (PTT)
Read: Anytime.
Write: Anytime.
Field
23.0.5.18 Port T Input Register (PTIT)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
ECT
7–0
7–0
W
W
associated pin values.
R
R
1
PTIT7
PTT7
IOC7
Data Direction Port K
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
—
7
0
7
on PORTK after changing the DDRK register.
= Unimplemented or Reserved
PTIT6
PTT6
IOC6
—
0
6
6
Figure 23-20. Port T Input Register (PTIT)
Figure 23-19. Port T Data Register (PTT)
Table 23-20. DDRK Field Descriptions
Table 23-21. PTT Field Descriptions
PTIT5
PTT5
IOC5
—
5
0
5
PTIT4
PTT4
IOC4
—
0
4
4
Description
Description
PTIT3
PTT3
IOC3
—
3
0
3
PTIT2
PTT2
IOC2
—
0
2
2
PTIT1
PTT1
IOC1
—
1
0
1
PTIT0
PTT0
IOC0
—
0
0
0