MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 230
MC9S12XDP512MAG
Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512MAG.pdf
(1348 pages)
Specifications of MC9S12XDP512MAG
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Chapter 6 XGATE (S12XGATEV2)
BFINSI
Operation
!RS1[w:0]
Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD starting
at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using
R0 as a RS1, this command can be used to set bits.
CCR Effects
Code and CPU Cycles
230
N:
Z:
V:
C:
BFINSI RD, RS1, RS2
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
w = (RS2[7:4])
o = (RS2[3:0])
V
0
Source Form
RD[w+o:o];
—
C
15
15
15
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
Bit Field Insert and Invert
TRI
7
0
1
W4
1
5
W4=3, O4=2
1
4
0
3
3
Machine Code
2
RD
O4
Inverted Bit Field Insert
0
0
0
RS1
RS2
RS1
RD
BFINSI
RS2
Freescale Semiconductor
1
1
Cycles
P
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