W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 81

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Smart Card interface register bit map, continued
14. SERIAL IRQ
W83627SF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA
interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame.
14.1 Start Frame
There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode.
In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tri-
states it. This brings all the states machines of the peripherals from idle to active states. The host
controller will then take over driving IRQSER signal low in the next clock and will continue driving the
IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4
to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock and
then tri-states it.
In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line
information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset,
the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start
frame.
14.2 IRQ/Data Frame
Once the start frame has been initiated, all the peripherals must start counting frames based on the
rsing edge of the start pulse. Each IRQ/Data Frame is three clocks long: Sample phase, Recovery
phase, and Turn-around phase.
During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the
corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the
BDLAB
BDLAB
+ 6
+ 7
+ 0
= 1
+ 1
= 1
ADDRESS
REGISTER
BASE
Reserved
Extended
Baudrate
Baudrate
Register
Control
Divisor
Divisor
Latch
Latch
High
Low
ECR Warm reset
BHL
BLL
Bit 0
Bit 8
0
direction
SCIO
Bit 1
Bit 9
1
CLKSTP
Bit 10
BIT NUMBER
Bit 2
2
- 81 -
CLKSTPH
Bit 11
Bit 3
3
frequency
select 0
SCCLK
Bit 12
Bit 4
Publication Release Date: May 31, 2005
4
frequency
select 1
SCCLK
Bit 13
Bit 5
5
clock base
W83627SF
sampling
select 0
Internal
Bit 14
Bit 6
6
Revision A1
clock base
sampling
select 1
Internal
Bit 15
Bit 7
7