W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 35

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
6.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the
TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
to test the UART in a convenient way.
bit is internally connected to the modem control input DCD .
connected to the modem control input RI .
(bit 0 of HCR)
Aside from the above connections, the UART operates normally. This method allows the CPU
RI and IRQ enable ( bit 3 of HCR)
7
0
DSR , RTS ( bit 1 of HCR)
0
6
5
0
4
3
2
1
- 35 -
0
DCD .
CTS , Loopback RI input ( bit 2 of HCR)
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Publication Release Date: May 31, 2005
W83627SF
Revision A1