W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 108

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

CRF3 (GP60-GP63 I/O selection register. Default 0xFF Bit 7-4: Reserved)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF4 (GP60-GP63 data register. Default 0xFF Bit 7-4: Reserved)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF5 (GP60-GP63 inversion register. Default 0x00 Bit 7-4: Reserved)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
CRF6 (GP70-GP74 I/O selection register. Default 0xFF Bit 7-5: Reserved)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF7 (GP70-GP74 data register. Default 0xFF Bit 7-5: Reserved)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF8 (GP70-GP74 inversion register. Default 0x00 Bit 7-5: Reserved)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
CRF9 (VID input data register. Bit 7 - 5: Reserved)
This register is read only. It contains original VID value.
CRFA (VID output data register)
This register allows user to configure different VID value. It can be read or written.
Bit 7 – 5 : Reserved.
Bit 4 – 0 : Original VID value.
Bit 7
Bit 6 – 5 : VID guarding bits. The corresponding power on setting pins are GP56, 66 and their
BIT 6
0
0
1
1
: Select VID code tables.
= 0old VID code table.
= 1new VID code table.
values are latched on the rising edge of PWROK signal.
BIT 5
0
1
0
1
-108-
3 units constraint
4 units constraint
5 units constraint
No constraint
LIMIT
W83627SF