W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 57

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Bit 2-0: These five bits are at high level during a read and can be written
8.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
Bit 7-5: These bits are read/write and select the mode.
000
001
010
011
100
101
110
111
CNFGB[5:3]
000
001
010
011
100
101
110
111
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to
tri-state the data lines and reading the data register returns the value on the data lines
and not the value in the data register.
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel
port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into
the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto
transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse
direction), bytes are moved from the ECP parallel port and packed into bytes in the
ecpDFifo.
Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
7
reflect other IRQ resources selected by PnP register (default)
6
5
4
3
- 57 -
2
IRQ RESOURCE
1
0
IRQ10
IRQ11
IRQ14
IRQ15
IRQ7
IRQ9
IRQ5
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Publication Release Date: May 31, 2005
.
W83627SF
Revision A1