W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 37
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W83627SF-AW
Manufacturer Part Number
W83627SF-AW
Description
Manufacturer
Winbond
Datasheet
1.W83627SF-AW.pdf
(116 pages)
Specifications of W83627SF-AW
Pin Count
128
Lead Free Status / RoHS Status
Not Compliant
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6.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
Bit 4, 5: Reserved
Bit 3:
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
BIT 7
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
a logical 0 by itself after being set to a logical 1.
a logical 0 by itself after being set to a logical 1.
other bits of UFR are programmed.
0
0
1
1
When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
7
BIT 6
0
1
0
1
6
5
TABLE 6-3 FIFO TRIGGER LEVEL
4
3
2
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
1
- 37 -
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: May 31, 2005
01
04
08
14
W83627SF
Revision A1
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