W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 27

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

5.5
This register is used to control the FIFO functions of Smart Card interface.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
Bit 5 - 3: Reserved.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will be
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will be
Bit 0: This bit enables FIFO of Smart Card interface. This bit should be set to a logical 1 before other
5.6
The Smart Card Control Register controls and defines the parity bit protocol for asynchronous data
communications.
BIT 7
Smart Card FIFO Control Register (SCFR, write only at "base address + 2")
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
cleared to a logical 0 by itself after being set to a logical 1.
cleared to a logical 0 by itself after being set to a logical 1.
bits of SCFR are programmed.
Smart Card Control Register (SCCR, write only at "base address + 3")
0
0
1
1
7
7
6
0
6
BIT 6
0
5
5
0
1
0
1
4
4
3
3
0
2
2
FIFO TRIGGER LEVEL
1
1
1
0
1
0
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
Parity Bit Enable (PBE)
Even Parity Enable (EPE)
Baud rate Divisor Latch Access Bit (BDLAB)
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FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: May 31, 2005
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W83627SF
Revision A1