W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 75

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

13.4 Interrupt Status Register (ISR, read only at "base address + 2")
This register reflects the Smart Card interface interrupt status, which is encoded by different interrupt
sources into 4 bits.
Bit 7, 6: These two bits are set to a logical 1 when SFR bit 0 = 1.
Bit 5: Reflect value of SCPSNT line status.
Bit 4: Set to 1 if SCPSNT toggles when this type of interrupt is enabled. Bit 0 of this register is also set
Bit 3 - 1: These three bits identify the priority level of the pending interrupt, as shown in the table
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
BIT
0
0
0
1
0
3
BIT
this bit will be set to a logical 0.
to 0 if this type of interrupt occurs.
below.
0
1
1
1
0
2
ISR
BIT
0
1
0
0
1
1
BIT
7
1
0
0
0
0
0
6
INTERRUPT
First
Second
Second
Third
PRIORITY
5
-
4
3
INTERRUPT CONTROL FUNCTION
Smart Card interface
Receive Status
RBR Data Ready
FIFO Data Timeout
INTERRUPT TYPE
TBR Empty
2
1
INTERRUPT SET AND FUNCTION
0
-
- 75 -
No interrupt pending
Interrupt status bit 0
Interrupt status bit 0
Interrupt status bit 0
SCPSNT toggle Interrupt (SCPTI)
SCPSNT line status
FIFO enabled
FIFO enabled
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active
level reached
No Interrupt pending
Data present in RX
FIFO for 4 characters
period of time since last
access of RX FIFO.
TBR empty
INTERRUPT
SOURCE
Publication Release Date: May 31, 2005
2. PBER =1
1. Read RBR
2. Read RBR until FIFO
data under active level
Read SCSR
Read RBR
1. Write data into TBR
2. Read ISR (if priority
is third)
CLEAR INTERRUPT
W83627SF
-
Revision A1