W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 5

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

14.
15.
16.
17.
18.
19.
20.
21.
13.8 Smart Card Status Register (SCSR, at "base address + 5") ............................................ 78
13.9 Extended Control Register (ECR, at "base address + 7") ................................................ 79
13.10 Baud rate divisor Latch High and Baud rate divisor Latch Low (BHL and BLL at "base
SERIAL IRQ ................................................................................................................................. 81
14.1 Start Frame ........................................................................................................................ 81
14.2 IRQ/Data Frame ................................................................................................................. 81
14.3 Stop Frame......................................................................................................................... 82
CONFIGURATION REGISTER ................................................................................................... 83
15.1 Chip (Global) Control Register ........................................................................................... 83
15.2 Logical Device 0 (FDC) ...................................................................................................... 89
15.3 Logical Device 1 (Parallel Port).......................................................................................... 92
15.4 Logical Device 2 (UART A) ................................................................................................ 93
15.5 Logical Device 3 (UART B) ................................................................................................ 93
15.6 Logical Device 5 (KBC) ...................................................................................................... 95
15.7 Logical Device 6 (CIR) ....................................................................................................... 96
15.8 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1)........................................ 96
15.9 Logical Device 8 (GPIO Port 2).......................................................................................... 97
15.10 Logical Device 9 (GPIO Port 3,4 are powered by standby source VSB)........................... 99
15.11 Logical Device A (ACPI)................................................................................................... 100
15.12 Logical Device B (Smart Card interface).......................................................................... 107
15.13 Logical Device C (GPIO Port 5,6,7 This power of the Ports is Source VCC) .................. 107
SPECIFICATIONS ..................................................................................................................... 109
16.1 Absolute Maximum Ratings ............................................................................................. 109
16.2 DC CHARACTERISTICS ................................................................................................. 109
APPLICATION CIRCUITS ......................................................................................................... 112
17.1 Parallel Port Extension FDD ............................................................................................ 112
17.2 Parallel Port Extension 2FDD .......................................................................................... 113
17.3 Four FDD Mode................................................................................................................ 113
ORDERING INSTRUCTION ...................................................................................................... 114
HOW TO READ THE TOP MARKING....................................................................................... 114
PACKAGE DIMENSIONS .......................................................................................................... 115
REVISION HISTORY ................................................................................................................. 116
address + 1" and "base address + 0" respectively when BDLAB = 1) ............................ 80
- 5 -
Publication Release Date: May 31, 2005
W83627SF
Revision A1