W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 32

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
BDLAB = 0
BDLAB = 0
BDLAB = 0
Register Address Base
+ 0
+ 0
+ 1
+ 2
+ 2
format) from the divisor latches of the baudrate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.
affected by this bit; the transmitter is not affected.
(Read Only)
(Write Only)
(Read Only)
(Write Only)
UART FIFO
Transmitter
Receiver
Register
Register
Interrupt
Register
Interrupt
Register
Register
Control
Control
Status
Buffer
Buffer
7
6
RBR
UFR
TBR
ICR
ISR
5
4
RBR Data
RX Data
TX Data
(ERDRI)
Interrupt
Interrupt
Pending
Enable
Enable
Ready
TABLE 6-1 UART Register Bit Map
FIFO
Bit 0
Bit 0
"0" if
3
0
2
(ETBREI)
RX Data
TX Data
Interrupt
Interrupt
Enable
Empty
Status
RCVR
Bit (0)
Reset
FIFO
1
Bit 1
Bit 1
TBR
1
BIT NUMBER
0
RX Data
TX Data
(EUSRI)
Interrupt
-32-
Interrupt
Enable
Status
Bit (1)
Reset
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
XMIT
FIFO
Bit 2
Bit 2
USR
2
RX Data
TX Data
Interrupt
(EHSRI)
Interrupt
Bit (2)**
Enable
Status
Select
Mode
DMA
Bit 3
Bit 3
HSR
3
Reserved Reversed
RX Data
TX Data
Bit 4
Bit 4
4
0
0
RX Data
TX Data
Bit 5
Bit 5
5
0
0
W83627SF
RX Data
TX Data
Enabled
Interrupt
FIFOs
Active
(LSB)
Level
Bit 6
Bit 6
RX
**
6
0
RX Data
TX Data
Enabled
Interrupt
(MSB)
FIFOs
Active
Level
Bit 7
Bit 7
RX
**
7
0