W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 31

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Smart Card interface register bit map, continued
6. UART PORT
6.1
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-
bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.
6.2
6.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
BDLAB
BDLAB
Register Address Base
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
= 1
+ 1
= 1
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
Register Address
Extended Control
Baudrate Divisor
Interrupt Enable
Baudrate Divisor
SMART CARD
SMART CARD
Latch High
Latch Low
Reserved
Register
Register
Register
Register
Control
Status
SCCR
SCSR
ECR
BHL
BLL
IER
Ready
(RDR)
Warm
RBR
Data
reset
Bit 0
Bit 8
0
1
0
direction
Overrun
(OER)
SCIO
Error
Bit 1
Bit 9
1
1
0
BIT NUMBER
Parity Bit
CLKSTP
(PBER)
Bit 10
Error
Bit 2
2
0
0
- 31 -
CLKSTPH
No Stop
Bit Error
(NSER)
Enable
Enable
(PBE)
Parity
Bit 11
Bit 3
IRQ
Bit
3
DETECTED
Publication Release Date: May 31, 2005
frequency
SILENT
SCCLK
select 0
Enable
(EPE)
(SBD)
Parity
BYTE
Bit 12
Even
Bit 4
4
0
y select 1
frequenc
(TBRE)
SCCLK
Empty
Bit 13
TBR
Bit 5
5
0
0
W83627SF
clock base
sampling
select 0
(TSRE)
Internal
Empty
Bit 14
TSR
Bit 6
6
0
0
Revision A1
Access Bit
clock base
Indication
Baudrate
sampling
(BDLAB)
RX FIFO
select 1
Internal
Divisor
(RFEI)
Bit 15
Latch
Error
Bit 7
7
0