W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 58

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

Bit 4: Read/Write (Valid only in ECP Mode)
Bit 3: Read/Write
Bit 2: Read/Write
Bit 1: Read only
Bit 0: Read only
8.3.11 Bit Map of ECP Port Registers
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
1
0
1
0
1
0
0
1
0
1
ecpAFifo
ecpDFifo
cnfgA
cnfgB
cFifo
data
tFifo
dsr
dcr
ecr
compress intrValue
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
nBusy
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Enables DMA.
Disables DMA unconditionally.
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts has
occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-
enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold
or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold
or more valid bytes to be read from the FIFO.
Addr/
PD7
RLE
D7
1
0
MODE
nAck
PD6
D6
1
0
Directio
PError
PD5
D5
0
1
Parallel Port Data FIFO
nErrIntrEn
ECP Data FIFO
ackIntEn
Select
PD4
Test FIFO
D4
Address or RLE field
1
1
-58-
SelectIn
dmaEn
nFault
PD3
D3
1
0
serviceIntr
PD2
nInit
D2
1
0
1
autofd strobe
PD1
D1
full
1
0
1
W83627SF
empty
PD0
D0
1
0
1
NOTE
2
1
1
2
2
2