W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 77

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

13.6 Smart Card Control Register (SCCR, write only at "base address + 3")
The Smart Card Control Register controls and defines the parity bit protocol for asynchronous data
communications.
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
Bit 6 - 5: Reserved. Always 0 when read.
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
Bit 2 – 0: Reserved. Bit 2 is always 0 and bit 1 – 0 are always 1 when read.
13.7 Interrupt Enable Register (IER, at "base address + 4")
This register contains global interrupt enable bit of Smart Card interface.
Bit 7 - 4: Reserved. Always 0 when read.
Bit 3: The Smart Card interface interrupt output is enabled by setting this bit to a logic 1.
Bit 2 – 0: Reserved. Always 0 when read.
format) from the divisor latches of the baudrate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
0
7
7
6
0
6
0
0
0
5
5
4
4
0
3
3
0
0
2
2
1
1
1
0
0
1
0
0
Parity Bit Enable (PBE)
Even Parity Enable (EPE)
Baud rate Divisor Latch Access Bit (BDLAB)
IRQ enable
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Publication Release Date: May 31, 2005
W83627SF
Revision A1