W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 46
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W83627SF-AW
Manufacturer Part Number
W83627SF-AW
Description
Manufacturer
Winbond
Datasheet
1.W83627SF-AW.pdf
(116 pages)
Specifications of W83627SF-AW
Pin Count
128
Lead Free Status / RoHS Status
Not Compliant
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TABLE: BAUD RATE TABLE, continued
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set.
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
7.1.10 Bank1.Reg2 - Version ID Register I (VID)
Power on default <7:0> = 0001,0000 binary
7.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR)
This register is defined same as in Bank0.Reg3.
7.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)
Power on default <7:0> = 0000,0000 binary
BIT
BIT
7-0
7-0
DESIRED BAUD RATE
(BANK0~3)
115200
19200
38400
57600
3600
4800
7200
9600
1.5M
NAME
NAME
TMRL
VID
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
READ/WRITE
READ/WRITE
Read/Write
Read Only
DECIMAL DIVISOR USED TO
GENERATE 16X CLOCK
1
32
24
16
12
Note 1
6
3
2
1
Timer Low Byte Register. This is a 12-bit timer (another
4-bit is defined in Bank1.Reg5) which resolution is 1 ms,
that is, the programmed maximum time is 2
timer is a down-counter. The timer start down count
when the bit EN_TMR (Enable Timer) of Bank0.Reg2. is
set to 1. When the timer down count to zero and
EN_TMR=1, the TMR_I is set to 1. When the counter
down count to zero, a new initial value will be re-loaded
into timer counter.
-46-
Version ID, default is set to 0x10.
BETWEEN DESIRED AND ACTUAL
DESCRIPTION
DESCRIPTION
PERCENT ERROR DIFFERENCE
0%
**
**
**
**
**
**
**
**
W83627SF
12
-1 ms. The
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