W83627SF-AW Winbond, W83627SF-AW Datasheet - Page 45

• Manufacturer Part Number: W83627SF-AW
• Manufacturer: Winbond

Specifications of W83627SF-AW

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

7.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR)
Power on default <7:0> = 0000,0000 binary
7.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode.
Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will
go to legacy UART mode and clear some register values shown table as follows.
BIT
4-0
DESIRED BAUD RATE
7
6
5
RXACT
RX_PD
Reserved
FOLVAL
134.5
1200
1800
2000
2400
110
150
300
600
50
75
NAME
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Read/Write
Read Only
-
Read Only
READ/WRITE
DECIMAL DIVISOR USED TO
GENERATE 16X CLOCK
TABLE: BAUD RATE TABLE
2304
1536
1047
857
768
384
192
96
64
58
48
Receive Active. Set to 1 whenever a pulse or pulse-
train is detected by the receiver. If a 1 is written into the
bit position, the bit is cleared and the receiver is de-
actived. When this bit is set, the receiver samples the
IR input continuously at the programmed baud rate and
transfers the data to the receiver FIFO.
Set to 1 whenever a pulse or pulse-train (modulated
pulse) is detected by the receiver. Can be used by the
software to detect idle condition Cleared Upon Read.
-
FIFO Level Value. Indicate that how many bytes are
there in the current received FIFO. Can read these bits
then get the FIFO level value and successively read
RBR by the prior value.
- 45 -
BETWEEN DESIRED AND ACTUAL
Publication Release Date: May 31, 2005
PERCENT ERROR DIFFERENCE
DESCRIPTION
0.099%
0.18%
0.53%
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W83627SF
Revision A1