XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 69

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
At the completion of this initial read cycle, the µC/µP has read in the contents of the first register or buffer
location (within the Framer) for this particular burst access operation. In order to illustrate how this burst I/O
cycle works, the byte (or word) of data, that is being read in
0x00. This indicates that the µC/µP is reading the very first register (or buffer location) in this burst access.
The procedure that the µC/µP must use to perform the remaining read cycles, within this Burst Access
operation, is presented below.
N
For subsequent read operations, within this burst cycle, the µC/µP simply repeats steps B.1 through B.3, as
illustrated in
The Burst I/O Access will be terminated upon the falling edge of the ALE_AS input signal. At this point the
Framer will cease to internally increment the latched address value. Further, the µC/µP is now free to execute
either a Programmed I/O access or to start another Burst Access Operation with the Framer.
Whenever a Motorola-type µC/µP wishes to write the contents of numerous registers or buffer locations over a
contiguous range of addresses, then it should do the following.
F
b. The output drivers of the bi-directional data bus (D[7:0]) are enabled. At some time later, the register or
a. The Framer internally increments the latched address value (within the Microprocessor Interface circuitry).
1.3.2.3.2.1.2
1.3.2.3.2.1.3
1.3.2.3.2.2
OTE
IGURE
B.0
B.1
B.2
B.3
buffer location corresponding to the incremented latched address value will be driven onto the bi-direc-
tional data bus.
: In order to insure that the Framer will interpret this signal as being a Read signal, the
WR_R/W input pin "High".
RDY_DTACK
13. M
Execute each subsequent Read Cycle, as described in steps B.1 through B.3, below.
Without toggling the ALE_AS input pin (e.g., keeping it "High"), toggle the RD_DS (Data Strobe) input
pin "Low". This step accomplishes the following.
After some settling time, the data on the bi-directional data bus will stabilize and can be read by the
µC/µP. The Framer will indicate that this data is ready to be read by asserting the RDY_DTACK
(DTACK) signal “Low”.
After the µC/µP detects the RDY_DTACK signal (from the Framer), it terminates the Read cycle by
toggling the RD_DS (Data Strobe) input pin "High".
ALE_AS
Figure 13
A[6:0]
D[7:0]
OTOROLA
WR
RD
CS
Write Burst Access: Motorola-Mode
Subsequent Read Operations
.
Terminating Burst Access Operation
µP I
Not Valid
NTERFACE
S
Offset = 0x01
Valid Data at
IGNALS
Address of Initial Target Register (Offset = 0x00)
,
DURING SUBSEQUENT
49
Figure 12
Not Valid
R
EAD
has been labeled Valid Data at Offset =
O
PERATIONS OF A
Offset = 0x02
Valid Data at
OCTAL T1/E1/J1 FRAMER
µC/µP
B
URST
XRT84L38
should keep the
I/O C
YCLE