XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 415

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
However, if the Transmit Data Link Byte Count value is zero, the framer will not force a flag sequence on to the
data link channel.
The table below shows configurations of the IDLE Insertion bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
If the ABORT bit of the Data Link Control Register is set, a BOS abort sequence (9 consecutive ones) is
transmitted on the data link channel following by all-one transmission. In other words, all data link bits will be
set to 1 after the transmission of the current message byte.
The table below shows configurations of the ABORT bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
Switching the data link channel from MOS mode to BOS mode while a message is being transmitted will
interrupt the message after the octet in progress is transmitted. If the MOS ABORT bit of the Data Link Control
Register is set, a MOS ABORT sequence (a zero followed by 7 ones) will be inserted before switching.
Switching the data link from BOS to LAPD will not take place until the current operation completes if Transmit
BOS byte count is not set to zero initially. If the Transmit BOS byte count value is set to zero, the transition
from BOS mode to MOS mode will take place right after finishing the current message octet.
The table below shows configurations of the MOS ABORT bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
13.1.3.2.5
The BOS Processor can generate a couple of interrupts indicating the status of BOS message transmission to
the microprocessor. These are the Transmit Start of Transfer (TxSOT) interrupt and the Transmit End of
Transfer (TxEOT) interrupt.
To enable these interrupts, the Transmit Start of Transfer Enable bit and the Transmit End of Transfer Enable
bit of the Data Link Interrupt Enable Register (DLIER) have to be set. In addition, the HDLC Controller Interrupt
Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
N
N
N
UMBER
UMBER
UMBER
B
B
B
2
3
6
IT
IT
IT
IDLE Insertion
MOS ABORT
Step 5: Enable transmit BOS message interrupts
B
B
B
ABORT
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
IT
IT
IT
R/W
R/W
R/W
T
T
T
YPE
YPE
YPE
0 - No flag sequence is sent on the data link channel.
1 - The framer forces a flag sequence of value 0x7E onto the data link
channel.
0 - No ABORT sequence is sent on the data link channel.
1 - The framer forces an ABORT sequence of pattern (111111111) onto the
data link channel. All data link bits will be set to 1 after sending the ABORT
sequence.
0 - The framer forces an MOS ABORT sequence of one zero and seven
ones (01111111) onto the data link channel during the transition from MOS
mode to BOS mode.
1 - No MOS ABORT sequence is sent on the data link channel during the
transition from MOS mode to BOS mode.
395
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38