XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 405

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The table below shows configurations of the Receive Red Alarm State Change Interrupt Enable bit of the Alarm
and Error Interrupt Enable Register (AEIER).
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER)
0X03H)
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
When these interrupt enable bits are set and Red Alarm is present in the incoming E1 frame, the XRT84L38
framer will declare Red Alarm by doing the following:
•
•
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Red Alarm State Change status bits of the Alarm and Error Status
Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
The Receive Red Alarm State bit of the Alarm and Error Status Register (AESR), on the other hand, is a read-
only bit indicating there is Red Alarm detected in the incoming E1 frame.
N
N
N
Set the read-only Receive Red Alarm State bit of the Alarm and Error Status Register (AESR) to one
indicating there is Red Alarm detected in the incoming E1 frame.
Set the Receive Red Alarm State Change bit of the Alarm and Error Status Register to one indicating there is
a change in state of Red Alarm. This status indicator is valid until the Framer Interrupt Status Register is
read.
UMBER
UMBER
UMBER
B
B
B
2
1
2
IT
IT
IT
Receive Red Alarm
Receive Red Alarm
Interrupt Enable
Alarm and Error
Interrupt Enable
State Change
State Change
B
B
B
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
IT
IT
IT
R/W
R/W
WC
T
T
T
YPE
YPE
YPE
0 - The Receive Red Alarm State Change interrupt is disabled. No Receive
Loss of Frame (RxLOF) interrupt will be generated upon detection of LOF
condition.
1 - The Receive Red Alarm State Change interrupt is enabled. Receive
Loss of Frame (RxLOF) interrupt will be generated upon detection of LOF
condition.
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
0 - There is no change of Red Alarm state in the incoming E1 payload
data.
1 - There is change of Red Alarm state in the incoming E1 payload data.
385
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
(INDIRECT ADDRESS = 0XNAH,
OCTAL T1/E1/J1 FRAMER
XRT84L38