XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 437

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
selected in Interrupt Control Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is
required to reset these status indicators.
The table below shows the Receive ABORT Sequence and Receive IDLE Flag Sequence status bits of the
Data Link Status Register.
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
Finally, the LAPD Controller generates Frame Check Sequence Error (FCS_ERR) interrupt when an erroneous
frame check sequence is detected at the end of a message or an IDLE flag is received that is not octet aligned.
To enable this interrupt, the Frame Check Sequence Error Detection Enable bit of the Data Link Interrupt
Enable Register (DLIER) have to be set. In addition, the HDLC Controller Interrupt Enable bit of the Block
Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Frame Check Sequence Error Detection Enable bit of the Data
Link Interrupt Enable Register.
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
When the Frame Check Sequence Error Detection interrupt enable bits is set and an erroneous frame check
sequence is detected at the end of a message, the LAPD Controller changes the Frame Check Sequence
Error Detection status bits of the Data Link Status Register (DLSR). This status indicator is valid until the Data
Link Status Register is read. Reading this register clears the associated interrupt if Reset Upon Read is
selected in Interrupt Control Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is
required to reset this status indicator.
The table below shows the Frame Check Sequence Error Detection status bits of the Data Link Status
Register.
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
13.2.4.1.2
When the LAPD Controller is receiving MOS message, the received message octets are written to the next
available receive data link buffer. The user is recommended to read Receive Data Link Byte Count Register for
next available receive data link buffer number.
N
N
N
UMBER
UMBER
UMBER
B
B
B
1
0
2
2
IT
IT
IT
Receive IDLE Flag
Detection Enable
Receive ABORT
Sequence Error
Sequence Error
Frame Check
Frame Check
Sequence
Sequence
Step 2: Find out the next available receive data link buffer
B
B
B
Detection
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
RUR /
RUR /
IT
IT
IT
R/W
WC
WC
WC
T
T
T
YPE
YPE
YPE
0 - There is no BOS ABORT sequence received in the data link channel.
1 - The HDLC Controller receives MOS ABORT sequence in the data link
channel.
0 - The message received in the data link channel is BOS message.
1 - The message received in the data link channel is MOS message.
0 - The Frame Check Sequence Error Detection interrupt is disabled.
1 - The Frame Check Sequence Error Detection interrupt is enabled.
0 - There is no FCS error detected in the data link channel.
1 - The HDLC Controller receives an erroneous FCS in the data link chan-
nel.
417
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38