XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 359

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
register array respectively. If 16-code signaling is selected in SF format, only the Signaling bit A and Signaling
Bit B positions are filled.
In ESF mode, the Receive Signaling Extraction Control [1:0] bits can select no signaling (transparent), two-
code signaling, four-code, or sixteen-code signaling. Two-code signaling decoding is done by stripping the
least significant bit (LSB) of the specific channel in frame 6, 12, 18 and 24 and stores it into the Signaling Bit A
position of RSRA register array. Four-code signaling is done by stripping the LSB of channel data in frame 6
and frame 18 and the LSB of channel data in frame 12 and 24, and store them into Signaling Bit A and
Signaling Bit B position of RSRA register array respectively. Sixteen-code signaling is implemented by
stripping the LSB of channel data in frames 6, 12, 18, and 24 and stores them into the Signaling Bit A,
Signaling Bit B, Signaling Bit C and Signaling Bit D position of RSRA register array respectively.
The table below shows configurations of the Receive Signaling Extraction Control [1:0] bits of the Receive
Signaling Control Register.
RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H)
Upon receiving and extraction of signaling bits from the incoming DS1 frames, the XRT84L38 framer compares
the signaling bits with the previously received ones. If there is a change of signaling data, a Signaling Update
(SIG) interrupt request may be generated at the end of a DS1 multi-frame. The user can thus be notified of a
Change of Signaling Data event.
To enable the Signaling Update interrupt, the Signaling Change Interrupt Enable bit of the Framer Interrupt
Enable Register (FIER) has to be set. In addition, the T1/E1 Framer Interrupt Enable bit of the Block Interrupt
Enable Register (BIER) needs to be one.
The table below shows configurations of the Signaling Change Interrupt Enable bit of the Framer Interrupt
Enable Register.
FRAMER INTERRUPT ENABLE REGISTER (FIER) (INDIRECT ADDRESS = 0XNAH, 0X05H)
The table below shows configurations of the T1/E1 Framer Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
N
N
N
UMBER
UMBER
UMBER
B
1-0
B
B
5
1
IT
IT
IT
Extraction Control
Signaling Change
Interrupt Enable
Interrupt Enable
T1/E1 Framer
B
B
B
Signaling
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
IT
IT
IT
R/W
R/W
R/W
T
T
T
YPE
YPE
YPE
00 - The XRT84L38 framer does not extract signaling information from
incoming DS1 payload data.
01 - The XRT84L38 framer extracts sixteen-code signaling information
from incoming DS1 payload data.
10 - The XRT84L38 framer extracts four-code signaling information from
incoming DS1 payload data.
11 - The XRT84L38 framer extracts two-code signaling information from
incoming DS1 payload data.
0 - The Signaling Update interrupt is disabled.
1 - The Signaling Update interrupt is enabled.
0 - Every interrupt generated by the Framer Interrupt Status Register
(FISR) is disabled.
1 - Every interrupt generated by the Framer Interrupt Status Register
(FISR) is enabled.
339
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38