XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 60

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Figure 6
during a Motorola-type Programmed I/O Read Operation.
Whenever a Motorola-type µC/µP wishes to write a byte or word of data into a register or buffer location, within
the Framer, it should do the following.
F
5. Further, the µC/µP should indicate that this cycle is a Read cycle by setting the
6. Next the µC/µP should initiate the current bus cycle by toggling the RD_DS (Data Strobe) input pin "Low".
7. After some settling time, the data on the bi-directional data bus will stabilize and can be read by the µC/µP.
8. After the µC/µP detects the RDY_DTACK signal (from the Framer) it will terminate the Read Cycle by tog-
1. Assert the ALE_AS (Address Select) input pin by toggling it "Low". This step enables the Address Bus
2. Place the address of the target register or buffer location (within the Framer), on the Address Bus input
3. While the µC/µP is placing this address value onto the Address Bus, the Address-Decoding circuitry (within
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate Address Setup time),
5. Further, the µC/µP should indicate that this current bus cycle is a Write operation by toggling the
6. The µC/µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
1.3.2.2.2.2
IGURE
"High".
This step enables the bi-directional data bus output drivers, within the Framer. At this point, the bi-direc-
tional data bus output drivers will proceed to drive the contents of the Address register onto the bi-direc-
tional data bus, D[7:0].
The Framer will indicate that this data can be read by asserting the RDY_DTACK (DTACK) signal “Low”.
gling the RD_DS (Data Strobe) input pin "High".
input drivers (within the Framer chip).
pins, A[6:0].
the user's system) should assert the CS (Chip Select) input pins of the Framer by toggling it "Low". This
step enables further communication between the µC/µP and the Framer Microprocessor Interface block.
the µC/µP should toggle the ALE_AS input pin "High". This step causes the Framer to latch the contents of
the Address Bus into its own circuitry. At this point, the Address of the register or buffer location (within the
Framer), has now been selected.
(R/W*) input pin "Low".
tional data bus, D[7:0].
6. M
RDY_DTACK
presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals
WR_R/W
ALE_AS
RD_DS
OTOROLA
A[6:0]
D[7:0]
CS
Motorola Mode Write Cycle
µP I
NTERFACE SIGNALS DURING A
Address of target Register
40
P
ROGRAMMED
Not Valid
I/O R
Valid Data
EAD
O
PERATION
WR_R/W
(R/W*) input pin
REV. 1.0.1
WR_R/W