XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 443

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
14.0 E1 HDLC CONTROLLER BLOCK
14.1
14.1.1
XRT84L38 allows user to insert data link information to outbound E1 frames. The data link information in E1
framing format mode can be inserted from:
•
•
•
The Transmit Data Link Source Select [1:0] bits, within the Synchronization MUX Register (SMR) determine
source of the data link bits to be inserted into the outgoing E1 frames.
The table below shows configuration of the Transmit Data Link Source Select [1:0] bits of the Synchronization
MUX Register (SMR).
SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H)
If the Transmit Data Link Source Select bits of the Transmit Data Link Select Register are set to 01, the
Transmit HDLC Controller block becomes input source of the data link bits in outgoing E1 frames.
Each of the eight framers within the XRT84L38 device contains an E1 Transmit High-level Data Link Controller
(HDLC) block. The function of this block is to provide a serial data link channel in E1 mode through the
following:
•
•
•
We will discuss how to configure XRT84L38 to transmit data link information through each of these data link
channels in later sections.
The E1 Transmit HDLC Controller block contains two major functional modules associated with E1 framing
formats. They are the LAPD Controller and the Bit-Oriented Signaling Processor.
There are two 96-byte transmit message buffers in shared memory for each of the eight framers to transmit
data link information. When one message buffer is filled up, the Transmit HDLC Controller automatically
switches to the next message buffer to load data link messages. These two message buffers ping-pong among
each other for data link message transmission.
The LAPD Enable bit of the Data Link Control Register (DLCR) determines whether the Transmit HDLC
Controller block should perform as the LAPD Controller or the BOS Processor.
N
E1 Transmit Overhead Input Interface Block
E1 Transmit HDLC Controller
E1 Transmit Serial Input Interface
The National bits (Sa4 through Sa8) of Timeslot 0 of non-FAS frame
Timeslot 16 octet when the framer is in Common Channel Signaling mode
D or E signaling timeslot channel
UMBER
B
3-2
IT
E1 Transmit HDLC Controller Block
Description of the E1 Transmit HDLC Controller Block
Source Select [1:0]
Transmit Data Link
B
IT
N
AME
B
IT
R/W
T
YPE
00 - The data link bits are inserted into the framer through the Transmit
Serial Data input Interface via the TxSer_n pins.
01 - The data link bits are inserted into the framer through the Transmit
HDLC Controller.
10 - The data link bits are inserted into the framer through the Transmit
Overhead Input Interface via the TxOH_n pins.
11 - The data link bits are inserted into the framer through the Transmit
Serial Data input Interface via the TxSer_n pins.
423
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38