XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 309

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
Clock input. The Receive High-speed Back-plane Interface of the framer then sends out serial data at rising
edge of the Receive Serial Clock. The local Terminal Equipment samples the serial data at falling edge of the
clock.
The Receive Single-frame Synchronization input signal (RxSync_n) should pulse HIGH at the beginning of the
256-bit frame indicating start of the frame. By sampling the HIGH pulse of the Receive Single-frame
Synchronization signal, the framer can identity the beginning of an E1 frame and start pumping payload data
out.
See
Interface block of the framer in MVIP 2.048Mbit/s mode.
The timing diagram of input signals to the framer when running at MVIP 2.048Mbit/s mode is shown in
Figure 88
F
F
IGURE
IGURE
RxChn[2]/RxChn
(RxSyncFrTD=1)
(RxSyncFrTD=1)
Figure 87
RxChn[1]/FrRxD
RxChn[0]/RxSig
RxSerClk(INV)
RxSync(input)
RxSync(input)
RxChClk(INV)
87. I
88. T
RxSerClk
.
RxChClk
RxChClk
(MVIP)
RxSer
NTERFACING
IMING
below for how to interface the local Terminal Equipment with the Receive Payload Data Output
F
D
IAGRAM OF
Equipment
XRT84L38
Terminal
I
NPUT SIGNALS TO THE
c1 c2 c3 c4 c5
1
2
Timeslot 1
TO LOCAL TERMINAL EQUIPMENT USING
3
4
A B
5
6
RxSerClk_0 (2.048MHz)
RxSer_0
RxMSync_0
RxSync_0
RxSerClk_7 (2.048MHz)
RxSer_7
RxMSync
RxSync_7
C
7
D
8
c1 c2 c3 c4 c5
1
1
2
2
Timeslot 2
3
3
289
4
4
F
A B
5
5
RAMER WHEN RUNNING AT
6
6
7
C
7
D
8
8
c1 c2 c3 c4 c5
1
2
Timeslot 3
3
4
A B
5
Data Input
Data Input
Interface
Interface
Receive
Payload
Receive
Payload
6
Chn 0
Chn 7
C
7
XRT84L38
MVIP 2.048M
D
8
OCTAL T1/E1/J1 FRAMER
MVIP 2.048M
BIT
/
1
c1 c2 c3 c4 c5
S DATA BUS
1
2
2
XRT84L38
BIT
Timeslot 4
3
3
4
4
/
S
5
5
A B
6
6
7
C
7
8
D
8