XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 414

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The table below shows how content of the Buffer Enable bit of the Transmit Data Link Byte Count Register
(TDLBCR) determines what the next available transmit data link buffer number is.
TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H)
13.1.3.2.2
After finding out the next available transmit data link buffer, the user should write the eight bits message that
are to be transmitted in the form (0d5d4d3d2d1d00) to the first location of the next available transmit data link
buffer. The writing of these buffers is through the LAPD Buffer 0 indirect data registers and the LAPD Buffer1
indirect data registers. LAPD Buffer 0 and 1 indirect data registers have addresses 0xn6H and 0xn7H
respectively. There is no indirect address register for transmit data link buffer 0 and 1.
A microcontroller WRITE access to the LAPD Buffer indirect data registers will access the transmit data link
buffer and a microcontroller READ will access the receive data link buffers. The very first WRITE access to the
LAPD Buffer indirect data register will always be direct to location 0 within the transmit data link buffer.
For example, if the BOS Message to be sent is (101011) and the next available transmit data link buffer of
Channel n is 1. The user should write pattern (01010110) into transmit data link buffer 1 of Channel n. The
following microprocessor access to the framer should be done:
WR
13.1.3.2.3
The user should program the value of message transmission repetitions into the Transmit Data Link Byte
Count Register. The framer will transmit the BOS message the same number of times as was stored in the
Transmit Data Link Byte Count Register (TDLBCR) before generating the Transmit End of Transfer (TxEOT)
interrupts. If the value stored inside the Transmit Data Link Byte Count Register (TDLBCR) is set to 0, the
message will be transmitted indefinitely and no Transmit End of Transfer interrupt will be generated.
The table below shows configurations of the Transmit Data Link Byte Count [6:0] bits the Transmit Data Link
Byte Count Register (TDLBCR).
TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H)
13.1.3.2.4
Configuration of the Data Link Control Register determines whether the BOS Processor will insert IDLE flag
character or ABORT sequence to the data link channel. It also determines how the transition between MOS
mode to BOS mode is done.
If the IDLE Insertion bit of the Data Link Control Register is set, repeated flags of value 0x7E are transmitted as
soon as the current operation is finished (defined by the value in Transmit Data Link Byte Count Register).
N
N
UMBER
UMBER
B
B
6-0
7
IT
IT
n7H
Transmit Data Link
Byte Count [6:0]
Buffer Select
Step 2: Write BOS Message into transmit data link buffer
Step 3: Program BOS Message transmission repetitions
Step 4: Configure BOS Message transmission control bits
B
B
56H
IT
IT
N
N
AME
AME
B
B
IT
IT
R/W
R
T
T
YPE
YPE
0 - The next available transmit data link buffer for sending out BOS or MOS
message is Buffer 0.
1 - The next available transmit data link buffer for sending out BOS or MOS
message is Buffer 1.
Value of these bits determines how many times a BOS message pattern
will be transmitted by the framer before generating the Transmit End of
Transfer (TxEOT) interrupt.
N
OTE
: If these bits are set to 0, the BOS message will be transmitted
indefinitely and no Transmit End of Transfer interrupts will be
generated.
394
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
REV. 1.0.1