XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 357

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The table below illustrates configurations of the Receive Data Conditioning Select [3:0] bits of the Receive
Channel Control Register (RCCR).
RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH)
When the Receive Data Conditioning Select [3:0] bits of the Receive Channel Control Register (RCCR) of a
particular DS0 channel are set to 0100, the received DS1 payload data of this DS0 channel are replaced by the
octet stored in the Receive User IDLE Code Register (RUCR). The table below shows contents of the Receive
User IDLE Code Register.
RECEIVE USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X97H)
10.4
N
N
UMBER
UMBER
B
3-0
B
7-0
IT
IT
How to Configure the XRT84L38 Framer to Apply Zero Code Suppression to Received DS1
Payload Data on a Per-Channel Basis
User IDLE Code
Conditioning
B
B
Receive
IT
Select
IT
N
N
AME
AME
B
B
IT
IT
R/W
R/W
T
T
YPE
YPE
0000 - The received DS1 payload data of this DS0 channel is unchanged.
0001 - All 8 bits of the input DS1 payload data of this DS0 channel are
inverted.
0010 - The even bits of the input DS1 payload data of this DS0 channel are
inverted.
0011 - The odd bits of the input DS1 payload data of this DS0 channel are
inverted.
0100 - The input DS1 payload data of this DS0 channel are replaced by
the octet stored in User IDLE Code Register (UCR).
0101 - The input DS1 payload data of this DS0 channel are replaced by
BUSY code (0x7F).
0110 - The input DS1 payload data of this DS0 channel are replaced by
VACANT code (0xFF).
0111 - The input DS1 payload data of this DS0 channel are replaced by
BUSY_TS code (111xxxxx).
1000 - The input DS1 payload data of this DS0 channel are replaced by
MUX-Out-Of-Frame (MOOF) code with value 0x1A.
1001 - The input DS1 payload data of this DS0 channel are replaced by
the A-law digital milliwatt pattern.
1010 - The input DS1 payload data of this DS0 channel are replaced by
the u-law digital milliwatt pattern.
1011 - The MSB bit of the input DS1 payload data of this DS0 channel is
inverted.
1100 - All bits of the input DS1 payload data of this DS0 channel except
MSB bit are inverted.
1101 - The input DS1 payload data of this DS0 channel are replaced by
PRBS pattern created by the internal PRBS Generator of XRT84L38
framer.
1110 - The input DS1 payload data of this DS0 channel is unchanged.
1111 - This channel is configured as D or E timeslot.
These READ/WRITE bit-fields permits the user store any value of IDLE
code into the framer. When the Receive Data Conditioning Select [3:0] bits
of RCCR register of a particular DS0 channel are set to 0100, the received
DS1 payload data are replaced by contents of this register and sent to the
Terminal Equipment.
337
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38