XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 264
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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XRT84L38
OCTAL T1/E1/J1 FRAMER
F
NINTH OCTET OF 16.384MBIT/S DATA STREAM
ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM
THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM
FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM
X
2. After the first octet of data is sent, the Receive High-speed Back-plane Interface insert seven octets (fifty-
3. Payload data of four channels are repeated and grouped together in a byte-interleaved way. The first pay-
4. The Receive High-speed Back-plane Interface also multiplexed signaling bits with payload bits and sent
X
Y
: F-bit of Channel X
: The Xth payload bit of Channel Y
six bits) of "don't care" data into the outgoing data stream.
load bit of Timeslot 0 of Channel 0 is sent first, followed by the second payload bit of Timeslot 0 of Channel
0 and so on. After all the bits of Timeslot 0 of Channel 0 is sent repeatedly, the Receive High-speed Back-
plane Interface will start sending the payload bits of Timeslot 0 of Channel 1 and 2. The payload bits of
Timeslot 0 of Channel 3 are sent the last. After the payload bits of Timeslot 0 of all four channels are sent,
it comes the payload bits of Timeslot 1 of Channel 0 and so on. The table below demonstrates how pay-
load bits of four channels are mapped into the 16.384Mbit/s data stream.
them together through the 16.384Mbit/s data stream. When the Receive High-speed Back-plane Interface
is sending the fifth payload bit of a particular channel, instead of sending it twice, it inserts the signaling bit
A of that particular channel. Similarly, the sixth payload bit of a particular channels is followed by the signal-
ing bit B of that channel; the seventh payload bit is followed by the signaling bit C; the eighth payload bit is
followed by the signaling bit D.
B
B
B
B
1
1
1
1
IT
IT
IT
IT
1
0
2
3
0
0
0
0
B
B
B
B
1
1
1
1
IT
IT
IT
IT
0
1
2
3
1
1
1
1
B
B
B
B
2
2
2
2
IT
IT
IT
IT
0
1
2
3
2
2
2
2
B
B
B
B
2
2
2
2
IT
IT
IT
IT
0
1
2
3
3
3
3
3
244
B
B
B
B
3
3
3
3
IT
IT
IT
IT
0
1
2
3
4
4
4
4
B
B
B
B
3
3
3
3
IT
IT
IT
IT
0
1
2
3
5
5
5
5
B
B
B
B
4
4
4
4
IT
IT
IT
IT
0
1
2
3
6
6
6
6
REV. 1.0.1
B
B
B
B
4
4
4
4
IT
IT
IT
IT
0
1
2
3
7
7
7
7
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