XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 416

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The table below shows configurations of the Transmit Start of Transfer Enable bit and the Transmit End of
Transfer Enable bit of the Data Link Interrupt Enable Register.
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
The table below shows configurations of the HDLC Controller Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
When these interrupt enable bits are set and the BOS message is transmitted to the data link channel, the
BOS Processor changes the Transmit Start of Transfer and Transmit End of Transfer status bits of the Data
Link Status Register (DLSR). These two status indicators are valid until the Data Link Status Register is read.
Reading these register clears the associated interrupt if Reset Upon Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Transmit Start of Transfer and Transmit End of Transfer status bits of the Data Link
Status Register.
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
13.1.3.2.6
A zero is then written into the LAPD enable bit of Data Link Control Register, which sets the transmitter to Bit-
Oriented mode and kicks off the transmission process. The LAPD Controller latches these control bits of the
Data Link Control Register and send a Transmit Start of Transfer interrupt (TxSOT) to the microprocessor to
indicate that a BOS message will be send. After the required number of times of BOS message is sent, the
LAPD Controller generates an Transmit End of Transfer interrupt (TxEOT) to the microprocessor to indicate
that the BOS message transmission comes to an end.
N
N
N
UMBER
UMBER
UMBER
B
B
B
6
4
3
6
4
IT
IT
IT
HDLC Controller
Transmit Start of
Transmit Start of
Transfer Enable
Transmit End of
Transfer Enable
Interrupt Enable
Transmit End of
Step 6: BOS message transmission
B
B
B
Transfer
Transfer
IT
IT
IT
N
N
N
AME
AME
AME
B
B
B
RUR /
RUR /
IT
IT
IT
R/W
R/W
R/W
WC
WC
T
T
T
YPE
YPE
YPE
0 - The Transmit Start of Transfer interrupt is disabled.
1 - The Transmit Start of Transfer interrupt is enabled.
0 - The Transmit End of Transfer interrupt is disabled.
1 - The Transmit End of Transfer interrupt is enabled.
0 - Every interrupt generated by the HDLC Controller is disabled.
1 - Every interrupt generated by the HDLC Controller is enabled.
0 - There is no data link message to be sent to the data link channel.
1 - The HDLC Controller will send a data link message to the data link
channel.
0 - No data link message was sent to the data link channel.
1 - The HDLC Controller finished sending a data link message to the data
link channel.
396
B
B
B
IT
IT
IT
D
D
D
ESCRIPTION
ESCRIPTION
ESCRIPTION
REV. 1.0.1