XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 313

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
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The Receive Back-plane Interface is pumping out data through RxSer_0 or RxSer_4 pins at 16.384Mbit/s. It
multiplexes payload and signaling data of every four channels into one data stream. Payload and signaling
data of Channel 0-3 are multiplexed onto the Receive Serial Data pin of Channel 0. Payload and signaling data
of Channel 4-7 are multiplexed onto the Receive Serial Data pin of Channel 4.
Free-running clocks of 16.384MHz are supplied to the Receive Serial Clock pin of Channel 0 and Channel 4 of
the framer. The Receive High-speed Back-plane Interface of the farmer provides data at rising edge of this
Receive Serial Clock. The local Terminal Equipment then latches incoming serial data at falling edge of the
clock.
The Receive High-speed Back-plane Interface maps four 2.048Mbit/s E1 data streams into this 16.384Mbit/s
data stream as described below:
FIRST OCTET OF 16.384MBIT/S DATA STREAM
SECOND OCTET OF 16.384MBIT/S DATA STREAM
X
1. Payload data of four channels are repeated and grouped together in a bit-interleaved way. The first pay-
2. The Receive High-speed Back-plane Interface also multiplexed signaling bits with payload bits and sent
Y
Receive Single-frame Synchronization Input signal (RxSync_n)
Receive Input Clock (RxInClk_n)
Receive Time-slot Indication clock (RxTSClk_n)
Receive Time Slot indicator bits (RxTSb[4:0]_n)
: The Xth payload bit of Channel Y
load bit of Timeslot 0 of Channel 0 is sent first, followed by the first payload bit of Timeslot 0 of Channel 1
and 2. The first payload bit of Timeslot 0 of Channel 3 is sent last.
After the first bits of Timeslot 0 of all four channels are sent, it comes the second bit of Timeslot 0 of
Channel 0 and so on. The table below demonstrates how payload bits of four channels are mapped into
the 16.384Mbit/s data stream.
them together through the 16.384Mbit/s data stream.
When the Receive High-speed Back-plane Interface is sending the fifth payload bit of a particular channel,
instead of sending it twice, it inserts the signaling bit A of that particular channel. Similarly, the sixth
payload bit of a particular channels is followed by the signaling bit B of that channel; the seventh payload
bit is followed by the signaling bit C; the eighth payload bit is followed by the signaling bit D.
B
B
1
2
IT
IT
0
0
0
0
B
B
1
2
IT
IT
0
0
1
1
B
B
2
IT
1
IT
1
1
2
2
B
B
2
1
IT
IT
1
1
3
3
293
B
B
1
2
IT
IT
2
2
4
4
B
B
1
2
IT
IT
2
2
5
5
OCTAL T1/E1/J1 FRAMER
B
B
1
2
IT
IT
3
3
6
6
XRT84L38
B
B
1
2
IT
IT
3
3
7
7