XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 302

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The following table demonstrates settings of the Receive Slip Buffer Slip bit, Receive Slip Buffer Empty bit and
Receive Slip Buffer Full bit of the Slip Buffer Status Register.
SLIP BUFFER STATUS REGISTER (SBSR) (INDIRECT ADDRESS = 0XNAH, 0X08H)
In this mode, the Receive Single-Frame Synchronization signal can be either input or output depending on the
settings of the Slip Buffer Receive Synchronization Direction bit of the Slip Buffer Control Register. When the
Slip Buffer Receive Synchronization Direction bit is set to 0, the Receive Single-Frame Synchronization signal
(RxSync_n) is an. When the Slip Buffer Receive Synchronization Direction bit is set to 1,the Receive Single-
Frame Synchronization signal (RxSync_n) is an input.
If the Receive Single-Frame Synchronization signal is an output, it should pulse HIGH for one E1 bit period
(488ns) at the last bit position of each E1 frame. By triggering on the HIGH pulse on the Receive Single-frame
Synchronization signal, the Terminal Equipment can identify the end of an E1 frame and should prepare to
accept payload data of the next E1 frame from the framer.
If the Receive Single-Frame Synchronization signal is an input, it should pulse HIGH for one E1 bit period
(488ns) at the first bit position (F-bit) of each E1 frame. By sampling the HIGH pulse of the Receive Single-
frame Synchronization signal, the framer should identity the beginning of an E1 frame and can send out data in
a synchronized way. It is the responsibility of the local Terminal Equipment to align the start of an E1 frame with
the Receive Single-Frame Synchronization pulse.
The Receive Multi-frame Synchronization signal should pulse HIGH for one E1 bit period (488ns) at the last bit
position of Frame number one of an E1 multi-frame. By triggering on the HIGH pulse on the Receive Multi-
frame Synchronization signal, the framer can identify the end of an E1 super-frame and should prepare to
accept payload data of the next E1 super-frame from the framer.
N
UMBER
B
2
1
1
IT
Buffer Empty
Receive Slip
Receive Slip
Receive Slip
Buffer Slip
Buffer Full
B
IT
N
AME
B
IT
R/W
R/W
R/W
T
YPE
0 - The Receive Slip Buffer is not full.
1 - The Receive Slip Buffer is full and one frame of data is discarded.
0 - The Receive Slip Buffer is not empty.
1 - The Receive Slip Buffer is empty and one frame of data is repeated.
0 - The Receive Slip Buffer does not slip.
1 - The Receive Slip Buffer slips since either full or emptied.
282
B
IT
D
ESCRIPTION
REV. 1.0.1