XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 360

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
When these interrupt enable bits are set and the signaling information received is changed, the DS1 Receive
Framer block will set the Signaling Updated status bit of the Framer Interrupt Status Register (FISR) to one.
This status indicator is valid until the Framer Interrupt Status Register is read. Reading this register clears the
associated interrupt if Reset-Upon-Read is selected in Interrupt Control Register (ICR). Otherwise, a write-to-
clear operation by the microprocessor is required to reset these status indicators.
The table below shows the Signaling Update status bits of the Framer Interrupt Status Register.
FRAMER INTERRUPT STATUS REGISTER (FISR) (INDIRECT ADDRESS = 0XNAH, 0X04H)
Now, there is only one problem remains. Since there are twenty-four DS0 channels in DS1, how do we know
signaling information of which channel is changed?
To solve this problem, the XRT84L38 provides three 8-bit Signaling Change Registers to indicate the
channel(s) which signaling data change had occurred over the last DS1 multi-frame period. Each bit of the
Signaling Change Registers represents one timeslot of the DS1 frame. If any particular bit is zero, it means
there is no change of signaling data occurred in that particular timeslot over the last DS1 multi-frame period. If
any particular bit is one, it means there is change of signaling data occurred over the last DS1 multi-frame
period.
The table below shows configurations of the Signaling Change Registers.
SIGNALING CHANGE REGISTERS (SCR) (INDIRECT ADDRESS = 0XN0H, 0X0DH - 0X0FH)
By reading contents of the Signaling Update status bits of the Framer Interrupt Status Register and the
Signaling Change Registers, the user can clearly identify which one(s) of the twenty-four DS0 channels has
changed signaling information over the last multi-frame period.
Depending on configurations of the XRT84L38 framer, the signaling bits can be extracted from the incoming
DS1 frame and direct to all or any one of the following destinations:
•
•
•
The follow sections discuss how to configure the XRT84L38 framer to extract signaling information bits and
send them to different destinations.
10.5.1.1
The four least significant bits of the Receive Signaling Register Array (RSRA) of each timeslot can be used to
store received signaling data. The user can read these bits through microprocessor access. If the XRT84L38
framer is configure to extract signaling bits from incoming DS1 payload data, the DS1 Receive Framer block
will strip off the least significant bits of signaling frames and store them into appropriate locations of the RSRA.
N
Signaling data is stored to Receive Signaling Register Array (RSRA) of each channel
Signaling data is sent to the Terminal Equipment through the Receive Signaling Output pin (RxSig_n)
Signaling data is embedded into the output PCM data sending towards the Terminal Equipment through the
Receive Serial Output pin (RxSer_n)
UMBER
0
0xn0H - 0x0EH
0xn0H - 0x0FH
L
B
XN
5
OCATION
IT
0H - 0
X
Signaling Updated
\ B
0DH
Store Signaling Bits into RSRA Register Array
IT
B
IT
N
AME
Ch 16
B
C
Ch 8
IT
H
0
7
B
RUR /
IT
WC
Ch 17
B
C
Ch 9
T
IT
YPE
H
1
6
0 - There is no change of signaling information in the incoming DS1 pay-
load data.
1 - There is change of signaling information in the incoming DS1 payload
data.
Ch 10
Ch 18
B
C
IT
H
2
5
340
Ch 19
Ch 11
B
C
IT
H
3
4
B
Ch 12
Ch 20
B
C
IT
IT
H
D
4
3
ESCRIPTION
Ch 13
Ch 21
B
C
IT
H
5
2
Ch 14
Ch 22
B
C
IT
H
6
1
REV. 1.0.1
Ch 15
Ch 23
B
C
IT
H
7
0